As is well known, integrated circuits have input and output pins that respectively receive data into the circuit and output data from the circuit. In some integrated circuits, such as the Synchronous Dynamic Random Access Memory (SDRAM) 10 illustrated in FIG. 1, the data pins are combined to operate as input/output pins (i.e., DQ pins). In an SDRAM for example, the input/output pins DQx 11 are designed to input or output data from or to a bus 14, which receives or sends the data to another useful device such as a microprocessor 12 having similar input/output pins 13. Of course, the pins 11, 13 do not operate as inputs and outputs simultaneously; when one set (11) is acting as outputs, the other set (13) will act as inputs.
Given this arrangement, it is preferable that the output circuitry of one device (say, the SDRAM 10), be impedance matched to the input circuitry of the receiving device (i.e., the microprocessor 12). As is known, when the output impedance of the output circuitry on the sending device is matched to the input impedance of the input circuitry on the receiving device, the transfer of the data is more efficient and less noisy, as impedance-based reflections are mitigated through such matching.
To facilitate such impedance matching, it is known to calibrate the output impedance of the output circuitry in an integrated circuit. Known output impedance calibration circuitry 20 is illustrated in FIG. 2. As shown, the circuitry 20 as implemented in an integrated circuit includes output pads 28 (i.e., “DQ pads,” or “I/O pads,” although only their functionality when used as output pads will be discussed further). The output pads 28, or bond pads, provide a surface for coupling the integrated circuit to a lead frame (and eventually a pin 11 on the circuit's package) via a bond wire as is well known. Data is driven to the output pads 28 via output drivers 26. Because an integrated circuit will typically have several different output pads 28 (specifically, “Y” pads as shown), it will have a corresponding number of output drivers 26 as well.
Calibrating the output impedance at the pads 28 comprises calibrating the output impedance of the output drivers 26, which occurs in conjunction with an output model 22 and a state machine 24. As can be seen from FIG. 2, the state machine 24 provides control signal 30 on a bus to the output drivers 26, and also feeds these control signals 30 back into the output model 22.
Before discussing how the control signals 30 are generated by the output model 22 and the state machine 24, the output drivers 26 which receive the control signals 30 are first discussed with reference to FIG. 3. The input to the output driver 26 is generally provided by an output buffer or latch earlier in the output data path of the integrated circuit. As shown, the output driver circuit 26 generally comprises a number of legs 25 (“X” number of legs are shown). Each leg 25 comprises, in series, two P-channel transistors 15, 17 and two N-channel transistors 19, 21. Notice that the inner transistors 17 and 19 are gated in parallel by the input from the output latch, and, as one skilled in the art will understand, transistors 17 and 19 thus act to drive the data to the output pad 28 in inverted fashion. That is to say, parallel-wired transistors 17 and 19 essentially form a large inverter.
Transistors 15 and 21, by contrast, are enable transistors for the power (Vdd) and ground portions of the legs 25, and in effect determine which leg or leg portions will participate in driving the output. As shown, each of the X legs 25 are driven by the control signals 30 generated by the state machine 24. Because there are X P-channel transistors 15 and X N-channel transistors 21, there are a total of 2X control signals 30, with control signals 30a controlling the P-channel transistors 15 and control signals 30b controlling the N-channel transistors. However, more or fewer control signals can be used, and even a single control signal can be used in other useful embodiments.
The output impedance at the output pad 28 is modified, or calibrated, by selecting various of the enable transistors 15 and 21. For example, to minimize the output impedance to the greatest extent, state machine 24 would enable all of the enable transistors 15 and 21 (i.e., control signals 30a would be low, while control signals 30b would be high). Because the enable transistors, when on, provide parallel paths between the output pad 28 and the power supply nodes, Vdd and GND, the output impedance is minimized. Thus, when all P-channel enable transistors 15 are active, the impedance for outputting a logic ‘1’ is minimized to its lowest extent, and when all N-channel enable transistors 21 are active, the impedance for outputting a logic ‘0’ is minimized to its lowest extent. Should the output impedances for either logic state need to be higher, fewer than all of the enable transistors 15 or 21 would be enabled by the control signals 30a or 30b, as will be explained in further detail below. Should the output be “tri-stated” so as to output neither a logic ‘0’ or ‘1,’ as would be typical when the pad 28 was acting as an input, no enable transistors 15 or 21 would be enabled.
Thus, calibration of the output impedance is controlled by the control signals 30, which are in turn generated by the output model 22 and the state machine 24, which are shown in further detail in FIG. 4. As shown, the output model 22, as its name suggests, models the output drivers 26, and hence preferably has the same structure: a parallel-wired inverter with X legs, in which each leg includes P- and N-channel enable transistors. Each of the enable transistors receives the same control signals 30 as do the output drivers 26 (see FIG. 2).
Because the output model 22 is indicative of the structure of the true output drivers 26, the logic in the state machine 24 uses the output model 22 (prior to useful operation of the integrated circuit) to set the control signals 30, in effect setting the output impedances of the output drivers 26 during useful operation. To do this, output enable control 32 of the state machine 24 sends various combinations of the control signal 30a and 30b to the output model 22, and gauges its output impedance by comparing its output voltage (Vout) to a reference voltage (Vref) at an operational amplifier 31. Vref (shown here as generated as part of the output enable control 32) and resistor R are chosen so that proper output impedance is achieved when Vout equals Vref.
Thus, the output enable control 32 initially disables the N-channel transistors (Vbias2 low; Vbias1 low), and enables the various P-channel enable transistors via control signals 30b in different combinations until Vout equals Vref. (Resistor R enable control signal NR would be asserted during this assessment). In this regard, note that the widths of the transistors in the various legs of the output model 22 (and the output driver circuitry 26) may be varied (e.g., exponentially, with leg 1 having a relative width of 1, leg 2 having a relative width of 2, leg three having a width of 4, etc.) to allow the output impedance to varied over a continuum by binarily incrementing the control signals on bus 30a (from 0001 to 0010, to 0011, etc.). In any event, using this scheme, the output enable control 32 might determine for example that the second and fourth legs 25 of the output drivers 26, corresponding to control signals PE2 and PE4 in FIG. 3, need to be enabled for proper output impedance.
After the optimal control enable signals 30a for the P-channel enable transistors are set in this fashion, the proper enablement of the N-channel enable transistors are then set by the control enable logic 32. Thus, while keeping the same optimal P-channel enable transistors enabled (e.g., PE2 and PE4), the output enable control 32 steps through various combinations of the control signals 30a to enable the N-channel enable transistors. (Resistor R enable control signal NR would not be asserted during this assessment). Again, the condition Vout equals Vref (in which Vref may be a different value than when earlier optimizing the P-channel transistors) sets the optimal combination of N-channel enable transistors. For example, the output enable control 32 might determine that proper output impedance would occur when enabling the third and fifth legs 25 of the output drivers 26, corresponding to control signals NE3 and NE5 in FIG. 3.
Therefore, to summarize, output enable control 32 might determine that enablement of control signals PE2 and PE4 (30b) are optimal for outputting a logic ‘1,’ and the enablement of control signals NE3 and NE5 (30a) are optimal for outputting a logic ‘0,’ and thus would send these control signals to the various output drivers 26 during useful operation when these logic states need to be output.
While such output impedance calibration circuitry 20 is functional, it may not be optimal when applied to some modern day, high speed integrated circuits. FIG. 5 shows a typical layout of an integrated circuit 10 having various output pads 28 and their associated output drivers 26. In the example shown, there are 32 such pads 28 and drivers 26, indicating a x32 device, and the pads/drivers are situated near the outer periphery of the integrated circuit 10. (They could also appear elsewhere along the integrated circuit, such as in a line through its center, etc.). Consistent with the output impedance calibration scheme discussed earlier, the integrated circuit 10 also contains the output model 22 and state machine 24 to generate the output enable control signals 30 received by each output driver 26, which may occur anywhere on the layout of the circuit 10.
But the output model 22 may not be perfectly indicative of the structure of the actual output drivers 26. This is because, despite best efforts during processing, the process can and normally will vary across the circuit 10. Thus, the various layers in the circuit may have different thickness across the expanse of the circuit, the transistors may have different line widths, etc. Ultimately, such process variations cause the electrical characteristics of the circuitry to also vary. For example, assume that process variations cause the transistors near the upper left corner of the circuit to have larger line widths than otherwise comparable transistors in the lower right corner. If we assume that the transistors as appear in the output model 22 are of normal size, those in output driver 261 for example would by comparison have larger line widths (more resistive), while those in output driver 2632 would have smaller line widths (less resistive).
Accordingly, when the state machine 24 attempts to discern the optimal settings for the output enable control signals 30 to calibrate the output impedance, the result will be that the output impedance at output pad 281 is too high, while that at output pad 2832 will be too low. Thus, while a device such as microprocessor 12 (FIG. 1) coupled to the circuit 10 will expect the same output impedance of all signals sent via bus 14, that goal may not be attainable, as thus the different signals on the bus 14 will suffer different reflection characteristics, hampering performance.
Accordingly, the art would be benefited by a solution to this problem, and is provided herein.